In recent years, storage devices, such as memory systems or storage systems, that use nonvolatile memories, such as NAND type flash memory devices (hereinafter, referred to as “NAND devices”), are widely used, as high-speed storage devices faster than hard disks, in information processing apparatuses, such as servers.
NAND devices are controlled by a NAND controller. Furthermore, a host and the NAND controller are connected by, for example, a Peripheral Component Interconnect (PCI) express. Instead of using the PCI express, a Serial Advanced Technology Attachment (SATA), a SAS I/F (Serial Attached Small Computer System Interface (SCSI) interface), or the like may also be used.
In a conventional technology, the band width of data transfer is increased by performing a parallel access on buses for multiple channels between a NAND controller and NAND devices.
For example, the flow of a read process performed in a conventional channel is as follows. Namely, a NAND controller interprets a read command received from the host and issues a read command to a specified NAND device. Then, the NAND device outputs read data and then the NAND controller stores the data in a buffer included in the NAND controller. Thereafter, the NAND controller transfers the read data to the host from a buffer.
There is a conventional technology that reduces the read time period by overlapping data-read commands when an initialization process is performed. Furthermore, there is another conventional technology that switches, by a memory controller, from parallel control to interleave control at high temperatures. Furthermore, there is another conventional technology that improves the performance of a data transfer process by changing the configuration of data burst when data burst transmission is performed.    Patent Document 1: Japanese Laid-open Patent Publication No. 2005-266888    Patent Document 2: Japanese Laid-open Patent Publication No. 2012-018648    Patent Document 3: Japanese Laid-open Patent Publication No. 2011-107928
However, when NAND devices are used, a busy time period for outputting data is long. Consequently, in a conventional read process or write process, because execution of a process needs to be waited during a busy time period, the use efficiency of a bus for each channel is low and thus the transfer efficiency of data is low.
Furthermore, even if the conventional technology that overlaps data-read commands is used when an initialization process is performed, in the read process or write process performed at the time of initialization, it is not possible to overlap the commands during the busy time period; therefore, it is difficult to improve the use efficiency of a bus. Furthermore, even if the conventional technology that switches from parallel control to interleave control at high temperatures, it is difficult to determine, in a controller, whether data can be overlapped. Consequently, because a busy time period is not efficiently used, it is difficult to improve the use efficiency of a bus. Furthermore, even if the conventional technology that changes the configuration of data burst, data transfer is not performed during a busy time period; therefore, it is difficult to improve the use efficiency of a bus. Consequently, it is difficult to improve the use efficiency of a bus even if any conventional technologies are used.